1. Field of the Invention
The present invention relates generally to data storage and more particularly to control circuitry for selectively writing to and reading from Magnetic Random Access Memory (MRAM) units.
2. Description of the Prior Art
A wide range of presently available media for data storage vary in several attributes including access speed, duration of reliable storage, and cost. Static Random Access Memory (SRAM) is the storage medium with the best access speed for the cost in applications such as cache memories. However, SRAM is volatile, meaning that it only maintains storage while power is continuously applied. Accordingly, computer users endure lengthy waits when they power-up their computers while substantial amounts of data are written from non-volatile but slow media, such as magnetic disks, into much faster random access memory (SRAM).
Flash memory has been proposed as an alternative to SRAM. Flash memory is a solid-state storage medium that provides moderate access times and that is non-volatile. Flash memory has the disadvantage that it has a limited lifetime, on the order of one million cycles per cell, after which a cell can no longer be written to. This lifetime is orders of magnitude too short for a random access memory in most modern computing system.
Another solid-state storage medium is Magnetic Random Access Memory (MRAM), which employs a Magnetic Tunnel Junction (MTJ) formed of layers of magnetic material. FIG. 1 shows a cross-section of a prior art MRAM unit 10 including an MTJ 12 formed of a pinned layer 14 and a free layer 16, which are magnetic layers typically formed of ferromagnetic materials, and a thin dielectric layer 18 disposed between layers 14 and 16. Pinned layer 14 has a magnetic moment orientation 20 that is fixed from rotating, while free layer 16 has a magnetic moment orientation 22 that is free to rotate in response to external magnetic fields. Methods of pinning a pinned layer 14 are well known in the art and include the use of an adjacent antiferromagnetic layer (not shown).
In an MRAM unit 10, a bit of data is encoded in the direction of the magnetic moment orientation 22 of the free layer 16 relative to the magnetic moment orientation 20 of the pinned layer 14. As is well known in the art, when the two magnetic moment orientations 20, 22 are parallel the resistance measured across the MTJ 12 is relatively low, and when the two magnetic moment orientations 20, 22 are antiparallel the resistance measured across the MTJ 12 is relatively high. Accordingly, the relative state of the magnetic moment orientations 20, 22, either parallel or antiparallel to one another, can be determined by reading the resistance across the MTJ 12 with a read current. Typical read currents are on the order of 1-50 xcexcA.
In an MRAM unit 10, the state of the bit, parallel or antiparallel and representing 0 or 1, for example, is varied by applying a write current Iw, typically on the order of 1-25mA, through two conductors, a bit line 24 and a digit line 26, situated proximate to the MTJ 12. The intensity of the write current applied to the bit line 24 may be different than that applied to the digit line 26. The bit line 24 and the digit line 26 cross one another at right angles above and below the MTJ 12. As is well known in the art, although the pinned layer 14 is depicted in FIG. 1 as nearer to the bit line 24, an MRAM unit 10 also functions with the pinned layer 14 nearer to the digit line 26.
As is well known, a magnetic field develops around an electric current in a wire. Accordingly, two magnetic fields arise when write currents Iw are simultaneously applied to both the bit line 24 and the digit line 26. The two magnetic fields combine at the free layer 16 to determine the magnetic moment orientation 22. The magnetic moment orientation 22 of the free layer 16 is made to alternate between the parallel and antiparallel states by alternating the direction of the write current Iw in either the bit line 24 or the digit line 26. Alternating (by a write control circuit, not shown) the direction of the write current Iw in one of the lines 24, 26 reverses the direction of the magnetic field around that conductor and thereby reverses the direction of the combined magnetic field at the free layer 16.
In an MRAM unit 10, the state of the bit is read by passing a read current IR through the MTJ 12. In these designs a transistor 30 is used to allow the read current IR to flow through the MTJ 12. during a read operation while preventing the write current Iw from flowing through the MTJ 12 during a write operation.
A control signal is required to determine which direction the reversible write current Iw will flow. Another control signal is required to change the state of the transistor 30 for read and write operations. Accordingly, what is desired is a read/write logic control circuit and write current direction circuit for an MRAM unit 10 that does not require additional logic compared with existing volatile memory media and can therefore allow MRAM units to be readily integrated into the existing RAM products.
A write control circuit for a magnetic tunnel junction MRAM provides a digit line and a bit line. The digit line includes a first end electrically connected to a first write current source by a first write transistor controlled by a first write logic gate, a first write current sink electrically connected to the first end by a first sink transistor controlled by a first sink logic gate, a second end electrically connected to a second write current source by a second write transistor controlled by a second write logic gate, a second write current sink electrically connected to the second end by a second sink transistor controlled by a second sink logic gate, and a segment proximate to the magnetic tunnel junction MRAM having a first direction. The bit line includes a third write current source electrically connected to a first end, a third write current sink electrically connected to a second end, and a segment proximate to the magnetic tunnel junction MRAM having a second direction oriented approximately 90xc2x0 to the first direction.
The write control circuit advantageously places one write current source and one write current sink on either end of the digit line to allow the write current to flow through the digit line in either direction. The direction of the write current in the digit line determines the orientation of the associated magnetic field and thereby determines the orientation of a magnetic moment of a free layer of the magnetic tunnel junction.
In the write control circuit the first and second write transistors can be p-channel MOS transistors and the first and second write logic gates can be NAND gates. In such embodiments the first write logic gate can be configured to accept first and second logic signals and the second write logic gate can be configured to accept the first logic signal and the inverse of the second logic signal. Similarly, the first and second sink transistors can be n-channel MOS transistors and the first and second sink logic gates can be NOR gates, and likewise the first sink logic gate can be configured to accept first and second logic signals and the second sink logic gate can be configured to accept the first logic signal and the inverse of the second logic signal. These embodiments are advantageous because they allow for the use of only two logic signals to selectively establish an electrical path between either write current source and the write current sink on the other end of the digit line.
A read/write control circuit for a magnetic tunnel junction MRAM provides a digit line and a bit line as described above where a read current source is electrically connected to the first end of the bit line by a first read transistor. A first surface of the magnetic tunnel junction MRAM is connected to the bit line between the first and second ends, and a second surface of the magnetic tunnel junction MRAM is connected to a read current sink by a second read transistor. The inclusion of the read current source and the read current sink to the previously described write control circuit further allows the invention to direct a read current through the magnetic tunnel junction MRAM.
In the read/write control circuit of the invention the third write transistor can be controlled by a first logic signal and the first read transistor can be controlled by an inverse of the first logic signal, allowing one logic signal to determine the current source connected to the bit line. Similarly, the third sink transistor can be controlled by a first logic signal and the second read transistor can be controlled by an inverse of the first logic signal so that one logic signal can determine whether the read current will flow through the magnetic tunnel junction or whether the write current will be directed past the magnetic tunnel junction to a write current sink.
A magnetic data storage unit of the invention provides a magnetic tunnel junction MRAM and digit and bit lines as described above. The magnetic tunnel junction MRAM can include a pinned layer electrically connected to the read current sink and located proximate to the digit line, a free layer electrically connected to the bit line, and a spacer layer disposed between the pinned and free layers. These embodiments provide a complete memory unit including a magnetic tunnel junction and a control circuit therefore.
A magnetic tunnel junction MRAM data storage device of the invention provides at least one digit line including a digit line transistor, at least one bit line including a bit line transistor, and at least one MRAM cell disposed proximate to one of the at least one digit line, electrically connected to one of the at least one bit line, and including a read current sink electrically connected to a magnetic tunnel junction by a read transistor. The at least one digit line includes first and second write current sources electrically connected to opposite ends of the at least one digit line and first and second write current sinks electrically connected to opposite ends of the at least one digit line. Similarly, the bit line includes a third write current source and a read current source each electrically connected to a first end of the at least one bit line and a third write current sink electrically connected to a second end of the at least one bit line. Additionally, the invention includes a column decoder configured to activate one of the at least one bit line by applying a first voltage to a gate of the digit line transistor and a row decoder capable of activating one of the at least one digit line by applying a second voltage to a gate of the digit line transistor. Lastly, the invention includes a read control line having a first end connected to the gate of the digit line transistor and a second end connected to a gate of the read transistor of the at least one MTJ cell. The read control line includes a read control line transistor disposed between the two ends, and a gate of the read control line is controlled by a first logic signal.